Logic synthesis CAD (computer-aided design) as a software tool to synthesize circuit data on actual transistor cell level, based on source code prepared by a designer, is used in digital logic circuit design using an electronic computer. The designer first prepares the source code by using a hardware description language (HDL) for description of circuit operation on level (or design abstraction level) called RTL (Register Transfer Level). This is termed RTL design, and, in the RTL design, the circuit operation is formed of combinations of flows of signals (or data transfer) from one to another of registers (e.g. flip-flops or the like) and their corresponding logic operations. The circuit data (or a net list) on the actual transistor cell level is created (or synthesized) by the logic synthesis CAD, based on operation description in the source code of the RTL design.
The logic synthesis CAD first performs conversion from the source code of the RTL design to gate-level intermediate data representing a logical expression corresponding to the source code. Mapping from gate level to transistor cell level (or technology library mapping) is performed based on the intermediate data, by using a technology library which predefines a gate circuit or a flip-flop provided by a semiconductor vendor. After that, transistor cell level circuit data is created through optimization for processing speed, circuit rightsizing, or the like, further by eliminating an unnecessary transistor cell or doing the like.
Although there may generally exist plural pieces of transistor cell level circuit data logically equivalent to the logical expression corresponding to the source code of the RTL design mentioned above, the logic synthesis CAD creates one of the plural pieces of transistor cell level circuit data through the above-described technology library mapping and optimization. However, the conventional logic synthesis CAD, although it can achieve optimization for circuit size, operating speed or power consumption, has no means for conveying designer's intention to the logic synthesis CAD, in a case where a CDC (Clock Domain Crossing) circuit in a system in which two or more clocks occur, or a multi-cycle path circuit designed with a longer cycle than a cycle of a specified clock, or the like is an object to be designed. Therefore, transistor cell level circuit data which is contrary to the designer's intention may possibly be synthesized. In other words, gate level circuit data which is logically equivalent but does not reflect the intent of design may be synthesized. As a result, there arises the problem of causing a circuit malfunction.